Raw interrupt status
| RXFIFO_FULL_INT_RAW | This interrupt raw bit turns to high level when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies. |
| TXFIFO_EMPTY_INT_RAW | This interrupt raw bit turns to high level when the amount of data in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. |
| PARITY_ERR_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a parity error in the data. |
| FRM_ERR_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a data frame error. |
| RXFIFO_OVF_INT_RAW | This interrupt raw bit turns to high level when the receiver receives more data than the capacity of RX FIFO. |
| DSR_CHG_INT_RAW | This interrupt raw bit turns to high level when the receiver detects the edge change of DSRn signal. |
| CTS_CHG_INT_RAW | This interrupt raw bit turns to high level when the receiver detects the edge change of CTSn signal. |
| BRK_DET_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a 0 after the stop bit. |
| RXFIFO_TOUT_INT_RAW | This interrupt raw bit turns to high level when the receiver takes more time than UART_RX_TOUT_THRHD to receive a byte. |
| SW_XON_INT_RAW | This interrupt raw bit turns to high level when the receiver receives an XON character and UART_SW_FLOW_CON_EN is set to 1. |
| SW_XOFF_INT_RAW | This interrupt raw bit turns to high level when the receiver receives an XOFF character and UART_SW_FLOW_CON_EN is set to 1. |
| GLITCH_DET_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a glitch in the middle of a start bit. |
| TX_BRK_DONE_INT_RAW | This interrupt raw bit turns to high level when the transmitter completes sending NULL characters, after all data in TX FIFO are sent. |
| TX_BRK_IDLE_DONE_INT_RAW | This interrupt raw bit turns to high level when the transmitter has kept the shortest duration after sending the last data. |
| TX_DONE_INT_RAW | This interrupt raw bit turns to high level when the transmitter has sent out all data in FIFO. |
| RS485_PARITY_ERR_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a parity error from the echo of the transmitter in RS485 mode. |
| RS485_FRM_ERR_INT_RAW | This interrupt raw bit turns to high level when the receiver detects a data frame error from the echo of the transmitter in RS485 mode. |
| RS485_CLASH_INT_RAW | This interrupt raw bit turns to high level when a collision is detected between the transmitter and the receiver in RS485 mode. |
| AT_CMD_CHAR_DET_INT_RAW | This interrupt raw bit turns to high level when the receiver detects the configured UART_AT_CMD CHAR. |
| WAKEUP_INT_RAW | This interrupt raw bit turns to high level when input RXD edge changes more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. |